Wu Zhipeng

About Me

I am currently a Lecturer at the School of Microelectronics, Tianjin University. I received my Ph.D. degree in Circuits and Systems from Tianjin University, advised by Prof. Yu Liu.

My research lies at the intersection of Electronic Design Automation (EDA), Computer Architecture, and Hardware–Software Co-design. I aim to bridge the gap between high-level algorithmic requirements and low-level hardware constraints through agile design methodologies and cross-layer optimization. Specifically, my work focuses on developing autonomous and controllable systems to tackle critical “bottleneck” challenges in intelligent edge computing.

My research has been featured in premier journals and conferences, including IEEE TCAD, JSA, IEEE CAL, IEEE ESL, ISCAS, and ISEDA.

Contact

• Email: zhipeng_wu@tju.edu.cn
• Lab Website: Laboratory Homepage

Research Interests

• EDA & Agile Hardware Design
  Automated toolchains and methodologies for reconfigurable spatial accelerators and custom DL accelerators.

• Computer Architecture
  RISC-V ecosystem, spatial architecture, and heterogeneous GPU+FPGA computing systems.

• Hardware-Aware Optimization
  Compiler-level scheduling and hardware-aware tensor computation frameworks.

News

• May 2025 — Our paper HAOT: Heterogeneous Hardware-Aware Tensor Computation Optimization Framework via Transformer has been accepted by IEEE TCAD!
• March 2025 — Our paper An Agile Design Method for Reconfigurable Spatial Accelerators in Tensor Computation was presented at ISEDA 2025, Hong Kong.
• January 2025 — Our paper Accelerating Control Flow on CGRAs via Speculative Iteration Execution has been accepted by IEEE CAL!
• December 2024 — Our paper HiEval: A Scheduling Performance Estimation Approach for Spatial Accelerators via Hierarchical Abstraction was published in Journal of Systems Architecture (JSA).